The present invention relates to the fabrication of integrated circuit devices on semiconductor substrates. In particular, the present invention relates to a high voltage CMOS FET device which allows scalability, and a method of fabricating such a device.
In complementary metal oxide semiconductor (CMOS) technology, a need to enhance the speed and increase the density of CMOS integrated circuits (ICs) has resulted in the evolution of transistor scaling, generally accompanied with the requirement of lowering the supply voltage proportionately. One of the key problems is the source-to-drain (S/D) punch through, which is pronounced when the S/D voltage is high and the field effect transistor (FET) channel length is short.
Several solutions to the problem of accommodating high S/D voltage have been devised. One such solution provides for the use of a V-gate FET (shown in FIG. 2 and discussed below). However, such a structure exhibits a lack of scalability, in particular in regard to the channel length. Another approach to address the high source to drain voltage issues is the U-gate FET (UFET), shown in FIG. 3 and discussed below. The major drawback presented by the UFET is the comers of the polysilicon gate under which the inversion channels might not be formed properly.